disability | Intern - Integrated Circuit Design in Stoughton, MA

Intern - Integrated Circuit Design

  • MIT Lincoln Laboratory
  • 26 Brock St
  • Stoughton, MA 02072
  • Full-Time
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Group 89--Quantum Information and Integrated Nanosystems GroupThe Quantum Information and Integrated Nanosystems Group conducts quantum information science research from a foundation of multiple diverse fabrication technologies. These include superconducting and trapped-ion qubits, classical superconducting circuits, complementary metal-oxide semiconductor (CMOS), and integrated photonics. These component technologies are used in synergy with quantum information science demonstrations.This position is for an integrated design intern working with our CMOS process technology. The candidate will develop foundry IP offerings (for example, standard cell libraries, memory IP, I/O libraries) and/or test circuits to be used for process monitoring and/or process performance demonstration vehicles. The candidate will perform some or all of schematic entry, circuit simulation, circuit layout, and layout verification. Depending on the type of circuit being developed, use of hardware description languages (HDLs) and/or commercial electronic design automation (EDA) software to assist with circuit synthesis and place and route may also be required. The candidate will work with multiple engineers having a variety of technical backgrounds in order to ensure a high quality of result and that design goals are met.The ideal candidate will be pursuing a bachelor??s or master??s degree in electrical engineering or a related field, and have completed at least one course in analog or digital VLSI circuit design. Familiarity with industry electronic design automation software, especially Cadence Virtuoso and Mentor Graphics Calibre, is desired but not required. The ability to work and communicate effectively in an interdisciplinary environment is a must. Requisition ID: 25043For Benefits Information, click Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required.
Associated topics: asic, board, cadence, design, design engineer, digital, engineer ii, h/w engineer, rf, semiconductor

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